Von Neumann Architecture

The stored-program model: one CPU, one memory holding both code and data, joined by a shared bus — and the bottleneck that follows.

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The von Neumann architecture is the blueprint behind almost every computer you have ever used. It has three parts — a CPU, a single memory, and I/O — all wired together by a shared system bus. Its defining idea is the stored-program concept: a program lives in the *same* read/write memory as its data. That one decision is why you can run a new program by loading bytes into memory instead of rewiring the machine.

Instructions and data share one memory

In a von Neumann machine, memory is just a long array of numbered words. A word holding the bits 10110000 might be an instruction or it might be the number 176 — memory itself does not know. The only thing that makes a word an instruction is that the CPU *fetched* it while looking for the next instruction to run. This uniformity is powerful: a program can even generate or modify code as data, because code and data are made of the same stuff in the same store.

Stored-program is the whole point

Before this idea, machines like ENIAC were 'programmed' by physically replugging cables. Putting the program *in memory* turned the computer into a general-purpose device: load different memory, get a different machine. That is the leap von Neumann's 1945 report crystallized.

The shared bus — and its bottleneck

The CPU reaches memory over the system bus: address lines to say *which* word, data lines to carry the value, and control lines to say *read* or *write*. Because instructions and data travel the *same* bus, the CPU cannot fetch an instruction and its data at the same time — they must take turns. This traffic jam is the famous von Neumann bottleneck, and it is the main reason fast on-chip caches exist.

1The CPU runs the program: a control unit decodes instructions, an ALU does arithmetic and logic, and registers hold working values.
2A single memory holds both instructions and data as numbered words.
3I/O moves data in and out of the world.
4One shared bus (address + data + control lines) carries every transfer — so code and data fetches serialize.

Harvard sidesteps it

The Harvard architecture gives instructions and data *separate* memories and buses, so the CPU can fetch an instruction and a data word in parallel. Modern CPUs are a hybrid: a von Neumann main memory, but split L1 instruction and data caches that behave Harvard-style up close.

OperationTimeSpace

Instruction fetch · uses the shared bus1 bus transfer—

Data load/store · competes with fetches — the bottleneck1 bus transfer—

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What is the von Neumann bottleneck?