Instruction Set Architecture (ISA)

The contract between software and hardware: which instructions exist, how they encode into bit fields, and the RISC-vs-CISC split.

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An instruction set architecture (ISA) is the agreed *contract* between software and a processor: exactly which instructions exist, what registers and memory model the programmer sees, and how each instruction is encoded as bits. It is the line where software stops and hardware begins — a compiler emits instructions the ISA defines, and any chip that implements that ISA must run them. x86-64, ARM, and RISC-V are ISAs; different chips implement each one differently underneath.

An instruction is just bit fields

Every instruction is a number, sliced into fields. An opcode field says *what* to do — add, load, jump — and operand fields say *what to act on*: register numbers, or a constant baked into the instruction. Decoding an instruction is literally pulling these slices apart.

A simple 16-bit ADD, fields packed left to right:

  opcode |  rd   |  rs   |  rt
  0001   | 010   | 011   | 100      (ADD r2, r3, r4)
  4 bits | 3 bits| 3 bits| 3 bits

  opcode 0001 = ADD
  rd = r2 (destination), rs = r3, rt = r4 (sources)

RISC vs CISC

Two design philosophies pull in opposite directions. RISC (Reduced Instruction Set Computer) keeps instructions few, simple, and fixed-width, and only special load/store instructions touch memory — everything else works register-to-register. CISC (Complex Instruction Set Computer) offers many powerful, variable-width instructions that can operate directly on memory, packing more work into each one.

The trade-off in one line

Fixed-width RISC instructions are trivial to fetch and pipeline — the next instruction always starts a fixed number of bytes along. Variable-width CISC instructions give denser code but are harder to decode, since you do not know an instruction's length until you start reading it. ARM, MIPS, and RISC-V are RISC; x86 is the classic CISC.

The line that lasts

An ISA is a *promise*: as long as a new chip honors it, decades-old binaries still run. That is why backward-compatible ISAs like x86 endure even as the silicon beneath them is redesigned generation after generation.

OperationTimeSpace

RISC decode · every instruction the same size — easy to pipelinefixed-width—

CISC decode · denser code, harder to decodevariable-width—

Check yourself

Why are fixed-width RISC instructions easier to pipeline than variable-width CISC ones?