Instruction Cycle

The CPU's heartbeat: fetch the next instruction, decode its opcode, execute it, and write the result back — millions of times a second.

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The instruction cycle is the heartbeat of a CPU. For *every* instruction in a program it repeats the same loop: fetch the instruction from memory, decode what it means, execute it, and write back any result. A whole program — billions of operations — is nothing more than this tiny cycle run over and over, millions of times a second.

The phases, step by step

1Fetch — the program counter (PC) holds the address of the next instruction. The CPU reads that memory word into the instruction register (IR), then increments the PC so it points at the following instruction.
2Decode — the control unit reads the instruction's opcode to work out which operation it is and which operands it needs.
3Execute — the operation runs: data flows through the ALU and registers and a result is produced (an add, a comparison, a memory address calculation).
4Write-back — the result is stored into a register or memory, completing the instruction. Then the cycle repeats from the new PC.

The PC drives everything

The program counter is what makes a program *flow*. Incrementing it after each fetch is why instructions run in order; a jump or branch simply writes a new value into the PC, and the next fetch picks up from there. Loops and ifs are just the PC being steered.

Inside fetch — the register dance

On a simple machine, fetch is a sequence of micro-operations moving data between registers: the PC's address goes out so memory can be read, the returned word lands in the IR, and the PC is bumped. A common shorthand is PC -> MAR, Memory[MAR] -> MBR -> IR, PC + 1 -> PC — where the MAR holds the address being accessed and the MBR holds the word coming back.

One instruction cycle:

  FETCH    PC -> MAR              ; address of next instruction
           Memory[MAR] -> MBR -> IR
           PC + 1 -> PC          ; advance to the following one
  DECODE   read IR opcode        ; what operation? which operands?
  EXECUTE  operands -> ALU -> result
  WB       result -> register/memory
  (repeat)

Phases, not equal time

Fetch, decode, execute, and write-back are *logical* steps, not equal-length ones. A simple register add executes in a flash; a memory load spends most of its time waiting on memory. Pipelining overlaps these phases across consecutive instructions to keep the hardware busy.

OperationTimeSpace

Per instruction · the four logical phasesfetch + decode + execute + WB—

Whole program · the same loop, repeatedmillions of cycles—

Check yourself

What does incrementing the program counter during the fetch phase accomplish?