The chain of hardware an instruction physically travels through — PC, instruction memory, register file, ALU, data memory, write-back — steered by the control unit.
The datapath is the physical chain of hardware an instruction travels through to get carried out. If the control unit is the conductor, the datapath is the orchestra: PC, instruction memory, register file, ALU, data memory, and the write-back path, all wired together with muxes that route data. The control unit raises the signals; the datapath is where the data actually moves.
The journey of one instruction
1Fetch — the PC (program counter) addresses instruction memory, and the instruction is read out.
2Decode / read operands — the register file reads out the source registers named in the instruction.
3Execute — the ALU (arithmetic logic unit) computes: it adds, subtracts, compares, or works out a memory address.
4Memory — for a load or store, data memory is read or written. Arithmetic instructions skip this step entirely.
5Write-back — the result, from the ALU or from data memory, is written back into the destination register in the register file.
Muxes are the steering wheels
A mux (multiplexer) is a selector switch: it passes one of several inputs through, chosen by a control signal. The classic example is the write-back mux — it picks whether the value written to a register comes from the ALU result (for an add) or from data memory (for a load). The control unit sets every mux select to route data correctly for the current instruction.
Single-cycle: the whole trip in one tick
In a single-cycle datapath, every instruction completes its *entire* journey — fetch through write-back — in one clock cycle. That is conceptually clean, but the clock must be slow enough for the *longest* instruction's path (often a load: instruction memory, then register read, then ALU, then data memory, then write-back). Faster designs split the work across cycles (multicycle) or overlap instructions (pipelining) so the slowest path no longer sets the clock for everyone.
Single-cycle datapath, an ADD vs a LOAD:
PC -> InstrMem -> RegFile(read) -> ALU -> [DataMem] -> RegFile(write)
| ^
ADD r1, r2, r3 : ALU computes r2+r3 ------- write-back mux picks ALU
LOAD r1, (r2) : ALU computes address -> DataMem -> mux picks memory
Control unit raises the signals; muxes steer ALU-result vs mem-data.
Datapath vs control unit
Keep the two roles straight. The datapath is the *where data flows* — registers, ALU, memories, wires, muxes. The control unit is the *what to do when* — it decodes the opcode and asserts the signals that open the right paths. Neither works without the other.
OperationTimeSpace
Single-cycle · clock set by the slowest instruction1 cycle/instruction—
Arithmetic op · ALU result goes straight to write-backskips data memory—
Load · longest path: the cycle-time setteruses data memory—
Check yourself
In a single-cycle datapath, what does the write-back multiplexer choose between?
