AlgoPlus//structures / pipeline
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Instruction Pipeline

Overlap five instructions across IF · ID · EX · MEM · WB — and handle the hazards.

Mode
Ideal
Cycle
Scenario
Legend
EX stage
Stall bubble
WB stage
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In a nutshell
A pipeline splits each instruction into five stages — fetch, decode, execute, memory, write-back — and works on five different instructions at once, one in each stage, like an assembly line. Once it is full, one instruction finishes every cycle instead of every five. The catch is hazards: when an instruction needs a result the one ahead of it has not produced yet, the pipeline must stall — or forward the result early to keep moving.
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Pipelining overlaps instructions across IF/ID/EX/MEM/WB like an assembly line, ideally finishing one per cycle. Data hazards force stalls; forwarding routes a result straight to the next instruction to avoid them.
Key terms
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